1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which can remove a skew occurring between data signals transmitted through global data input/output (IO) signal lines of different lengths, and a method for arranging signal lines thereof.
2. Discussion of the Related Art
A conventional semiconductor memory device typically includes a memory cell array region, a column decoder region, an IO control signal region, and a peripheral circuit region. The semiconductor memory device also includes local and global data IO lines for transmitting data signals from the memory cell array region to the IO control signal region. The local data IO lines are arranged in the same direction as word lines and are located above the memory cell array region. The global data IO lines are arranged in a direction perpendicular to the local data IO lines and are located above the memory cell array region and the column decoder region. Because lengths of the global data IO lines differ according to the location of the memory cell arrays the semiconductor memory device tends to have a skew between signals of those lines.
FIG. 1 is a schematic view illustrating a signal line arrangement of a conventional semiconductor memory device. As shown in FIG. 1, the semiconductor memory device includes a peripheral circuit 10, first and second memory cell arrays 21 and 22, a column decoder 30, and an IO control circuit 40. The semiconductor device also includes local data IO signal lines LIO and global data IO signal lines GIO0 to GIO3.
As shown in FIG. 1, non-hatched signal lines are arranged on a first layer, and hatched signal lines are arranged on a second layer. The IO control circuit 40 includes an IO sense amplifier (not shown) for amplifying signals to be inputted/outputted through the global data IO signal lines GIO-0 to GIO-3, a precharge circuit (not shown) for precharging the global data IO signal lines GIO-0 to GIO-3 in response to a precharge command, and a data IO multiplexer (not shown) for transmitting data signals between the IO sense amplifier and the global data IO signal lines GIO-0 to GIO-3.
The peripheral circuit 10, which may include a row decoder (not shown), decodes a row address to generate a word line selecting signal. The first and second memory cell arrays 21 and 22 write/read data to/from a memory cell (not shown) which is selected in response to a column selecting signal inputted from the column decoder 30 and the word line selecting signal inputted from the peripheral circuit 10. The column decoder 30 decodes a column address to output the column selecting signal. In addition, the column decoder 30 disables the column selecting signal in response to a precharge command inputted from the IO control circuit 40 during a precharge operation. The IO control circuit 40 amplifies the data signals inputted/outputted through the global data IO signal lines GIO-0 to GIO-3 and precharges the global data IO signal lines GIO-0 to GIO-3.
As further shown in FIG. 1, the column decoder 30 is arranged between the first and second memory cell arrays 21 and 22 and the IO control circuit 40 is arranged on an opposite side of the column decoder 30. The second memory cell array 22 is located between the IO control circuit 40 and the column decoder 30 and the peripheral circuit 10 is arranged on an upper side of the first and second memory cell arrays 21 and 22.
The local data IO signal lines LIO are arranged in a vertical direction on the first layer above regions of the first and second memory cell arrays 21 and 22, and the global data IO signal lines GIO-0 to GIO-3 are arranged horizontally and are placed in a vertical direction with respect to the local data IO signal lines LIO above the first and second memory cell array 21 and 22 regions and a region of the column decoder 30. The global data IO signal lines GIO-0 and GIO-2 are connected to the local data IO signal lines LIO above the first memory cell array 21 region, and the global data IO signal lines GIO-1 and GIO-3 are connected to the local data IO signal lines LIO above the second memory cell array 22 region.
If the global data IO signal lines GIO-0 to GIO-3 are arranged as shown in FIG. 1, a skew occurs between data outputted from the first and second memory cell arrays 21 and 22.
For example, data outputted from the first memory cell array 21 passes through the column decoder 30 region and the second memory cell array 22 region to reach the IO control circuit 40 through the global data IO signal lines GIO-0 and GIO-2. However, data outputted from the second memory cell array 22 directly reaches the IO control circuit 40 through the global data IO signal lines GIO-1 and GIO-3 without passing through the column decoder 30 region. Thus, a skew occurs between data outputted from the first and second memory cell arrays 21 and 22. The resulting skew can cause an abnormal operation of the semiconductor memory device if it exceeds, for example, a predetermined limit, and since the operation speed of the semiconductor device is high, the predetermined limit is smaller, thus an increase in the number of abnormal operations may occur.
Referring back to FIG. 1, during a precharge operation for precharging the global data IO signal lines GIO-0 to GIO-3 to a predetermined level, the column selecting signal outputted from the column decoder 30 should be disabled before the global data IO signal lines GIO-0 to GIO-3 are precharged. To do this, the column decoder 30 disables the column selecting signal in response to the precharge command outputted from the IO control circuit 40.
However, since the column decoder 30 is arranged between the first and second memory cell arrays 21 and 22, the column decoder 30 is farther from the IO control circuit 40 than the second memory cell array 22. Thus, the IO signal lines which exist in the second memory cell array 22 region may be precharged before the column selecting signal is disabled. As such, a need exists for a semiconductor memory device that can remove a skew between data signals transmitted through global IO signal lines and that efficiently precharges IO signal lines.